1. Field of the Invention
The present invention relates to pre-driver circuits and particularly to turning off the upper output device in such circuits.
2. Description of Background Art
In many tri-state pre-driver circuits, back-gate current blocking diodes in the pull-up path connected to the gate of an upper output transistor may prevent the transistor from turning completely OFF, thereby increasing both the dynamic operating current (Iccd) and the power dissipation capacitance (Cpd) of the device.
FIG. 1 is a schematic for a conventional pre-driver circuit 10 with In and Tri-state signal inputs and an input/output (I/O) pin. The circuit has blocking diodes 11 connected in the Vdd line to the back-gate of the circuit""s control transistors to prevent Ioff current from flowing into Vdd when a Vdd+vt voltage is applied to the input/output (I/O) pin during the tri-state condition. The pre-driver circuit has a p-channel upper output (UOP) transistor 100 and a n-channel lower output (LOP) transistor 101 with the drains being connected together through a ballast resistor 102, and the sources being connected between Vdd and Gnd, respectively. The circuit""s input/output (I/O) pin is taken off the drain of the UOP transistor 100. The blocking diodes 11, shown as a pn diode 111 in parallel with a Schottky diode 110, are connected between Vdd and the Vddref source line driving the transistor""s back-gates.
During normal operation of the circuit, when both the In and Tri-state signals are LOW, p-channel transistor 103 turns ON, coupling the Vdd signal through parallel blocking diodes 110 and 111 to the gate of the upper output transistor 100, thereby attempting to turn OFF output transistor 100. However, particularly in high frequency switching conditions, the voltage drop across these diodes can prevent the gate of the upper output transistor from pulling all the way up to the Vdd rail and completely turning OFF, thereby allowing an increase in the circuit""s dynamic operating current (Iccd). This in turn effectively increases the devices power dissipation capacitance (Cpd).
The Iccd current is given as
Iccd=(Cpd)*(Vdd)*fin+(iccdxe2x80x94static),
where
fin=the input frequency in Hz.
In many pre-driver circuits, the back-gate blocking diodes are by-passed to increase circuit speed during normal operation of the pre-driver circuit, while reducing Ioff current and satisfying over-voltage tolerant specifications.
FIG. 2 is a schematic for a conventional circuit that by-passes the back-gate current blocking diodes. The circuit consists of a conventional pre-driver circuit 20 and a blocking diode bypass circuitry 21. The pre-driver circuit 20 has a p-channel UOP transistor 200 and a n-channel LOP transistor 201 with drains connected together through a ballast resistor 202 and an I/O pin connected to the drain of p-channel transistor 200.
In the blocking diode circuit 21, transistors 211 and 214 are used to short around parallel pn/Schottky diodes 210/219 and provide Vdd directly to the back-gate source line Vddref, while p-channel transistors 217, 218, and 212 serve as the critical Ioff and over-voltage tolerant circuit components. Under normal operation, transistors 212, 217, 218 are in an OFF condition and inverter 215 supplies a low voltage to the gate of p-channel transistor 211 through n-channel transistor 214, thus supplying Vdd to Vddref line, bypassing the current blocking diodes 210/219. This provides a stable Vdd source at the back-gate of UOP transistor 200 and the back-gate and sources of the UOP p-channel pre-driver transistors 203 and 204, instead of Vdd minus the voltage drop across blocking diodes 210/219.
In this circuit, Ioff is the maximum leakage current into and out of the input/output transistors 200,201 when Vdd=0V and the I/O pin is forced to a given DC voltage. During the Ioff condition, n-channel transistor 216 is in an OFF condition, while p-channel transistors 217 and 218 are in an ON condition, shorting the I/O pin to S1 and S4 nodes, respectively. When the I/O pin is ramped to a given DC voltage, the voltage at node S1 through transistor 217 will assure that inverter 213 will pull node S2 to ground, thereby turning OFF n-channel transistor 214, releasing control of node S4 to the I/O pin through p-channel transistor 218. Notice that n-channel transistor 214 will never be in the ON condition during an Ioff condition since the Vdd source voltage to inverter 213 is 0 volts for this condition. The DC voltage on the I/O, pin through transistor 218, also assures that p-channel transistor 211 is in the OFF condition. Therefore, the Vddref line will track the given DC voltage on the I/O pin since transistors 212, 218, and 203 are all in the ON condition, thereby controlling the signal to the gate and back-gate of UOP p-channel transistor 200. When the I/O node is ramped during an Ioff test, the ramped signal is fed through transistors 212 and 218 to the gate and back-gate of UOP transistor 200, assuring that the UOP transistor 200 remains in an OFF condition, thereby reducing the Ioff current through UOP transistor 200.
These type circuits also must protect against over-voltage applied to the I/O pin while in the tri-state mode, satisfying standard over-voltage tolerant specifications. When the voltage on the disabled I/O pin is pulled to a voltage vt above Vdd, p-channel transistor 217 is in an ON condition and connects signal S1 to the I/O voltage, assuring that n-channel transistor 214 is in an OFF condition, thus giving control of the signal S4 to the I/O through p-channel transistor 218. Also, the voltage on the I/O pin will assure that p-channel transistor 211 remains in an OFF condition, thus eliminating the risk of any current sinking into Vdd through transistor 211. Also, in the tri-state mode, when an over-voltage (a voltage vt above Vdd) is applied to the disabled I/O pin, p-channel transistor 212 will be in an ON condition and the Vddref line will track the I/O pin voltage. Transistors 212 and 218 will supply the voltage on the I/O pin to back-gate of the UOP transistor 200, thus clamping the back-gate and drain of the UOP transistor. Also, transistors 212 and 218 supplies the voltage on the I/O pin to the back-gate and source of p-channel transistor 204, in the main pre-driver circuit, further assuring that the gate and drain of UOP transistor 200 does not turn ON and sink current into Vdd.
The conventional blocking diode by-pass and over-voltage tolerant circuit approach discussed above requires approximately as many components as the pre-driver circuit being improved. What is needed is an effective solution that requires a minimum number of additional components to by-pass the blocking diodes, reduce the Ioff current, and provide over-voltage tolerant protection. The embodiment of the present invention overcomes this need by providing these functions using only three additional components and, as a result is more efficient and more cost competitive to manufacture.
In its broader aspect, the present invention discloses a pre-driver circuit, which uses three additional components to (1) bypass the back-gate current blocking diodes, (2) lower the Ioff current, and (3) provide over-voltage tolerant protection in the pre-driver circuit. The circuit accomplishes these three characteristics by adding only three additional components, which is a 65% reduction in required circuitry over conventional approaches.
The solution disclosed in the present invention is unique because it uses the pre-driver""s tri-state input signal to control the pull-up path of the pre-driver circuit. This circuit by-passes the blocking diode (or diodes) found in many pre-driver circuit""s pull-up path, which is connected in the path to the gate of an upper output (UOP) transistor, preventing an increase in the power dissipation capacitance (Cpd) of the circuit. Particularly, in high frequency switching conditions, the removal of these diodes allows the gate of the UOP transistor to pull-up to the Vdd rail and as a result, completely turn off the UOP transistor, thereby preventing an increase in the dynamic operating current (Iccd) and the power dissipation capacitance (Cpd) of the device.